This invention relates to an improvement of an MIS-type field effect transistor.
For achieving a large scale integration (LSI), it is necessary to decrease the surface area of each of the semiconductor elements constituting an intergrated circuit (IC). Where MIS-type field effect transistors (FET) are included in the IC, the reduction of the surface area naturally results in the shortened channel region of the FET. However, a so-called "short channel effect" is generated if the channel region is made too short in a conventional MIS-type FET, resulting in difficulties with respect to the design and analysis of a large scale IC including such FET's . To be more specific, the threshold voltage of an MIS-type FET having a sufficiently long channel region is determined by the impurity, etc. introduced into the channel region, not by the length of the channel region. However, the threshold voltage depends to a large extent on the length of the channel region if the channel region is made unduly short, resulting in an enlarged variation of the threshold voltages among the FET's. Naturally, the enlarged variation presents a big problem to be solved in the manufacture of MIS-type FET's. Incidentally, the "short channel effect" is described in detail in L.D. Yau, "Solid State Electronics", Vol. 17, page 1,059, 1974 and Lee, "Solid State Electronics", Vol. 16, page 1,407, 1973.